1. Field of the Invention
The present invention relates in general to a flat panel display (FPD) and a fabrication method thereof. In particular, the present invention relates to a flat panel display with reduced parasitic capacitance and its fabrication method.
2. Description of the Related Art
Liquid crystal display (LCD) devices are a well-known form of flat panel displays with the advantages of low power consumption, light weight, thin profile, and low driving voltage. The liquid crystal molecules change orientation when an electronic field is applied. In the display region of the LCD, an array of pixel regions is patterned by horizontally extending gate lines and vertically extending data lines. Each pixel region has a thin film transistor (TFT) and a pixel electrode. The TFT serves as a switching device.
The traditional TFT array substrate is fabricated by the following method. A gate insulating layer, an amorphous silicon layer, an n+ doped silicon layer and a metal layer (i.e. M2) are sequentially formed on a substrate with a gate thereon. The metal layer (M2) is wet etched using a first resist layer to define a data line pattern, and the edge of the patterned metal layer undercuts the first resist layer. The first resist layer is continuously used to dry etch the n+ doped silicon layer and the amorphous silicon layer. After etching the metal, n+ doped silicon, and amorphous silicon layers, the first resist layer is then ashed to become a second resist layer with a channel pattern. The second resist layer is then used to be a mask to wet etch the metal layer again, and the edge of the metal layer (M2) is cut again. The second resist layer is continuously used to dry etch the n+ doped silicon layer to define a source and a drain.
In the above-mentioned etching processes, the metal layer (M2) is wet etched twice to cut its edge. The amorphous silicon layer, however, still has the same pattern as the first resist layer. Therefore, the to-be-formed pixel electrode cannot achieve a higher pixel aperture ratio from behind the edge of the metal layer (M2) because of parasitic capacitance between the pixel electrode and the n+ doped silicon layer.